Looking back at my FET idea, mostly for learning stuff, I was looking at that SOA graph for the FET I proposed and tried to follow along with this tutorial
here, though I'm not entirely sure I got it.
What does the horizontal axis, VDs Drain-Source voltage, represent in practice ? Does this mean the potential difference between D and S ? Taking my 48v battery as an example, with the FET "off", am I expected to see 48v if I measure across the FET ? Whereas with it "on" (saturated ?), there should be very little drop across it, since that's what you want a FET to do when fully on, so it dissipates as little power as possible, at least that's how I remember things.
That being said, when I slowly ramp up the gate voltage, I'm keeping the FET in its linear region where it dissipate a lot of power instead of being open...and eventually pops...