2-Layer PCB help..

[Super Nade]

Guys, do you think power traces laid out like this will cause problems?
Exclusion areas in the ground plane have not been defined yet.

Singals are all analog and have a max bandwidth of 100kHz i.e DC-100kHz.
Power traces are 0.05" and the IC's are all DIP.

[linuxguru]

Re: 2-Layer PCB help..

Depends on your signal traces - i.e. will they still be routable using just layer 1 and vias to crossover to layer 2? If you want to maximize the manufacturing yield, you should try to minimize the number of vias. The ideal number is zero vias, with all signal traces going from pad to pad on one layer only. In practice, this is difficult to achieve (some of Woz's designs for the Apple II managed to achieve this).

[Super Nade]

Re: 2-Layer PCB help..

Here is the updated version. Signal traces are on the bottom layer (green) while the power bus is on the top layer. I have not laid out the "keep out areas" on the ground plane. This is gonna be a 2-layer board, because anything else is beyond my budget. All ICs are DIPs. I still have to put in the bypass tantalums near every IC, place filter caps on the VCC/VEE power bus and add in Voltage limiting Zeners on the power bus and on the integrators to ensure low gain at DC.

http://img238.*************/img238/3...0152524cd4.png

[999999999]

Re: 2-Layer PCB help..

That should work but as for the layout, factor in some space for the decoupling caps. For example, around U2, move C3 and everything above it, up at least 100mil. Likewise depending on R10's wattage rating, it may be large enough you want to move R10 and everything below it, down 100mil (to allow decoupling cap to be nearest power pins). Same applies to U1 & U3, ideally you do not want to route everything then come back later adding the capacitors as an afterthought.