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Old 01-21-2022, 07:07 PM   #1
toomanydatsuns
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Join Date: Jan 2022
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Default Logic Board / Schematic for Apple Power Mac G5 "Late 2005" (A1117)

Hi all! So happy to have found this community.

I'm looking for a schematic or a board view of the logic board used by the "Late 2005" Apple Power Mac G5 Quad-core or Dual-core.

Apple uses identifiers 820-1628, 820-1628-A, and 661-3726 for this part.

Since the schematics seem very hard to find, I'm specifically interested in Apple's "U4 (Kodiak)" implementation of the IBM CPC945 northbridge, and particularly how Apple wired the memory controller pins.

There's tons of misinformation about this chip online, and I'd be very curious to see how Apple actually wired it, and how it differs from IBM's own implementation in something like the JS21.

I've attached a datasheet and design guide from IBM concerning the CPC945. Reading through these, it's not clear to me that there actually was a way in hardware to disable support for features of the 945's memory controller.

Apple glosses over it in their documentation, including a very confusing image of what looks like an RDIMM as their example of "compatible ECC memory" (see Service Source page 135).



Resources:
Power Mac G5 Developer Note (Oct 2005)

Service Source

User's Guide
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