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Old 02-25-2011, 08:14 AM   #1
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Exclamation Understanding bus values

Hi all!

This time I won't be burdening you with questions of experience and so, but pure theory is on on the hand right now.

I have difficulties understanding the bandwidth speed of FSB and HT, Wikipedia is cloudy too, so that I want to point out (and be verified) certain things.

I'm worried about the real speed, meaning MegaTransfers per Second (MT/s). By my knowledge, I say FSB (as in PIII) is calculated like this, for instance:

FSB of 100MHz x 1 x 8 = 800MB/s

Where 100MHz is the clock of the bus, 1 is the cycle length (I guess it may be compared to burst mode in DRAM technologies), 8 is the 8bytes of a 64bit width of the bus. This is clear to me, let's move on with the core2 extreme:

FSB of 400MHz x 4 x 8 = 12800MB/s

The very same as above, only increased values. Now let's move to the problem. Problem with HyperTransport 1.0 (1.1) to be specific.

FSB of 200MHz x 4 x 2 = 1600MB/s

Yes I know all of the FSB should be base clock or BCLK, but here's the thing: 200 is the clock, 4 is the HT1.0 multiplier and 2 is the DDR ability of the HT. I'm using MBs deliberately as the market does (with AMD it did so) instead of MT/s, because right now I'm confused - where in that pattern is the bus bit-width value? Since the hypertransport has a 16bit connections, I should add one more ''x 2'' to it, thus getting the correct values, no?

Then it would be total fo 3200MB/s (or MT/s). Then why the advetisemens always shows 1600MTs or 2000MTs if the HT multiplier is 5, not 4000MTs?

Need to know if I'm correct, also just wondering if these results (3200 & 4000) are uni-directional or bi-directional.

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Old 03-08-2011, 06:06 PM   #2
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Default Re: Understanding bus values

Then why the advetisemens always shows 1600MTs or 2000MTs if the HT multiplier is 5, not 4000MTs?
HT will change its speed at its own pace hence your not able to know the "set speed".
and quote
HyperTransport also facilitates power management as it is compliant with the Advanced Configuration and Power Interface specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies.
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Old 03-09-2011, 12:40 AM   #3
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Default Re: Understanding bus values

thank you for sharing.
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Old 03-09-2011, 05:46 AM   #4
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Default Re: Understanding bus values

why are we trying to apply hypertransport to core2? I think HT is only on AMD's side till the later core-ix series chips

or are we? wait, your question seems somewhat confusing
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Old 03-09-2011, 07:08 AM   #5
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Default Re: Understanding bus values


intel's "quad pumped" marketing crap is another factor btw..

CPUs with "800MHz" FSB are actually running on 200 "real" MHz.

- 400FSB -> 100MHz
- 533FSB -> 133MHz
- 800FSB -> 200MHz (kinda makes me wonder why there's no 166MHz/667FSB Oo)
- 1066FSB -> 266MHz
- 1333FSB -> 333MHz
- 1600FSB -> 400MHz

^this stuff started with the Pentium 4 and kinda ended with the Core 2 CPUs
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